1. Field of the Invention
The present invention relates to data communication methods used in serial data transfer systems, and more particularly, to a data communication method used in a serial data transfer system in which a master (sending unit) sends serial data to a slave (receiving unit) via, for example, an inter-integrated circuit (I2C) bus.
2. Description of the Related Art
As shown in FIG. 5, in a serial data transfer system for sending serial data via an I2C bus, at least two units, a unit (master) 1, which is a sending unit, and a unit (slave) 2, which is a receiving unit, are connected to each other using a serial data line (SDA line) 3 for transferring data and a serial clock line (SCL line) 4 for transferring clock signals. In the master 1 and the slave 2, SD represents a data sending terminal, RD represents a data receiving terminal, SC represents a clock sending terminal, and RC represents a clock receiving terminal.
As shown in FIG. 6, the master 1 transfers a start condition S from the data sending terminal SD and the clock sending terminal SC via the SDA line 3 and the SCL line 4 such that a data signal SDA and a clock signal SCL have a predetermined first phase relationship at the start of a frame, and also transfers a stop condition P such that the data signal SDA and the clock signal SCL have a predetermined second phase relationship at the end of the frame. The master 1 transfers n-byte data in synchronization with clocks between the start condition S and the stop condition P.
The slave 2 detects the start condition S from the data receiving terminal RD and the clock receiving terminal RC to start reception of a frame, and sends an acknowledgement A from the data sending terminal SD to the master 1 via the SDA line 3 every time one byte of data is received. The slave 2 identifies the end of the frame from the stop condition P.
In other words, the master 1 sends the start condition S to the slave 2. Then, the master 1 sends a slave address as the first bit to the seventh bit, and sends a read/write control signal R/W as the eighth bit. After receiving an acknowledgement A sent from the slave 2 as the ninth bit, the master 1 transfers n bytes as transmission data, receives an acknowledgement A sent from the slave 2 every time one byte of data is transferred to the slave 2, and sends the stop condition P at the termination of data transfer.
FIG. 7 explains the levels (L: low level or H: high level) of signals output to the SDA line 3 and the SCL line 4 from each of the master 1 and the slave 2 when communication is performed via an I2C bus. When the master 1 performs transmission to the slave 2, the slave 2 outputs an “H” signal to the SDA line 3 and the SCL line 4, as shown in FIG. 7(b), and the master 1 outputs an “H” signal and “L” signal to the SDA line 3 and the SCL line 4 in accordance with data and a clock signal, as shown in FIG. 7(a). When one of the master 1 and the slave 2 outputs an “H” signal to a line, if the other of the master 1 and the slave 2 outputs an “L” signal, the line represents “L”.
In other words, when the master 1 sends the start condition S, the SCL line 4 is “H” and the SDA line 3 is changed from “H” to “L”. When the master 1 sends the stop condition P, the SCL line 4 is “H” and the SDA line 3 is changed from “L” to “H”. Also, in order to receive an acknowledgement A, the master 1 outputs an “H” signal to the SDA line 3 as the ninth bit after sending a byte. In contrast, the slave 2 receives data sent from the master 1 to the SDA line 3 while outputting an “H” signal to the SDA line 3 and the SCL line 4, and outputs an “L” signal (“H” for NACK) to the SDA line 3 as the ninth bit after receiving the byte in order to send an acknowledgement A, as shown in FIG. 7(c). Also, after detecting the falling edge of the ninth clock bit, the slave 2 changes the SDA line 3 from “L” to “H”. The slave 2 detects the stop condition P to complete reception of the frame.
Noise interference or a waveform distortion may cause a clock difference between a transmitter and a receiver. With such a difference between the transmitter and the receiver, the receiver may terminate reception processing normally even if the transmitter detects a communication error in the final byte of a communication frame.
FIG. 8 explains a state in which the master 1 recognizes abnormal termination but the slave 2 recognizes normal termination. When the sixth bit clock is regarded as two clocks due to interference of a noise component N, which is shown in FIG. 8 (c), in the SCL line 4, the slave 2 regards the normal seventh bit as the eighth bit. Then, if a frame is received successfully, the slave 2 outputs ACK (=“L”) to the SDA line 3. Thus, the slave 2 regards the normal eighth bit as the ninth bit. After detecting the falling edge of the ninth bit, the slave 2 outputs an “H” signal to the SDA line 3.
In contrast, the master 1 receives an “H” signal on the SDA line 3 as NACK at the normal ninth bit (A bit). Then, the master 1 sends the stop condition P. Since the slave 2 outputs an “H” signal to the SDA line 3 and the SCL line 4, the stop condition P represented by a dotted line 15 appears on the SDA line 3 and the SCL line 4. The slave 2 detects the stop condition P to normally terminate processing.
As described above, in the case where a receiver normally terminates reception processing although a transmitter recognizes abnormal termination causes the following problems:                1) inconsistency of operation as a system;        2) possibility of unintentional operation; and        3) possibility of malfunction.        
For example, retransmission performed by a transmitter that terminates abnormally causes a problem described below. When an instruction for switching on a power supply is abnormally terminated, the transmitter resends the instruction to the receiver. Thus, the instruction for switching on the power supply is reported twice to the receiver. As a result of this, the receiver switches on the power supply in accordance with the first instruction, and then switches off the power supply in accordance with the second instruction. Thus, the receiver performs an operation that is not desired by the transmitter. Consequently, it is necessary for the receiver to recognize abnormal termination when the transmitter recognizes abnormal termination.
One approach for avoiding malfunction in I2C bus communication is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 9-265436. In this approach, in order to avoid a malfunction caused when a master (microcomputer) reads or writes data from or to a slave (nonvolatile memory) when an SDA line is “L”, the master performs an access operation after confirming that the slave releases a bus.
Also, a data transfer method for avoiding contention on a bus connecting a master to a slave is disclosed, for example, in Japanese Unexamined Patent Application Publication No. 2001-290764. In this approach, when the master performs transmission, the slave monitors whether or not data having a predetermined number of bytes is received from the master. When the data having the predetermined number of bytes is received, the data line is released, and the slave sends data to the master.
However, the known approaches described above do not solve the problems where the transmitter recognizes abnormal termination but the receiver recognizes normal termination.